The present invention relates to the field of integrated circuit analysis. More particularly, the present invention relates to integrated circuit defect analysis.
Integrated circuit (IC) design is a laborious and complex process that involves iterations of design development and takes into account a large number of constraints (e.g., power requirements, processing requirements, etc.). To facilitate the design process, computer modeling of the IC is commonly performed to study various performance characteristics of the proposed design. Even with a perfect design, however, the manufactured IC corresponding to the design may be less than perfect. Deviations between the design and manufactured versions of the IC may arise due to one or more factors, such as, a defect in the manufacturing process, a defect in the manufacture of a particular IC, manufacturing limitation(s) unforeseen during the design process, or real world limitations (e.g., material characteristics).
Depending on the defect, it is possible that even a single defect in a manufactured IC may render the entire IC defective. With present ICs containing upwards of billions of devices (e.g., resisters, capacitors, inductors, transistors, diodes, flip flops, etc.) along with the necessary connections there between to operate in a desired manner, identifying the source(s) of the defect within the IC is no easy task. One way to enable testing of manufactured ICs (to determine IC defects) is to include design for test (DFT) structures in the IC during the design process.
An example of DFT structures included in an IC is scan chains. A scan chain comprises flip flops (or other sequential devices) serially connected to each other, the output of one flip flop being the input of the next flip flop in the series. One or more such scan chains can be included in an IC. For each manufactured IC, an IC tester loads a pre-determined test pattern to each scan chain of the manufactured IC and correspondingly reads out a unload pattern from each scan chain. This is referred to as a scan test. One or more pre-determined test patterns may be inputted to each scan chain for the scan test. An unload pattern from a particular scan chain that differs from an expected pattern indicates the presence of a defect within that scan chain.
For each scan chain in which it's unload pattern differs from the expected pattern, the next step is to determine the location of the failure. Scan chain diagnostic is used to identify the exact location in the failing scan chain. Performing scan chain diagnostics uses the fail data collected from the IC tester to narrow down the failure location. Ideally the scan chain diagnostics should pinpoint the exact flip flop(s) within a scan chain that is defective. In practice, however, diagnosis of the scan chain defect is less precise.
Typically, any of a number of flip flops in a scan chain may be diagnosed as being defective, rather than a specific flip flop in the scan chain. The inability to pinpoint a particular flip flop may occur due to insufficiency of the test data. Another cause may be due to the IC design itself—the design making it difficult to distinguish between two bit positions of the flip flops or certain bit positions in a scan chain that can not be diagnosed. Because scan chain diagnosis identifies the failing flip flop(s) based on those flip flop(s) with the highest failure probability (e.g., weighted binary determination), the locations of flip flops dictated by the IC design can limit the ability to pinpoint a particular flip flop.
Diagnosis of scan chain defects is also computationally intensive. It requires performing circuit simulations using numerous pre-determined test patterns, analyzing the corresponding unload patterns, and iteratively adjusting the circuit simulation in an attempt to match the (fail) test data from the manufactured IC to those observed in the circuit simulations. Since each manufactured IC is tested and it can contain more than one scan chain, in volume diagnostic mode, this can be a high computational load.
Thus, it would be beneficial to provide a scan chain diagnostic tool that overcomes the difficulty in locating defects due to the IC design itself. It would be further beneficial to provide a simulation tool that enhances the accuracy and performance throughput of scan chain diagnostics in the post-manufacturing stage of the IC design process.